In wireless network applications, downloading of data, multimedia files and so on gradually becomes the mainstream of the applications, which results in a trend of obvious asymmetry in upstream and downstream communication services. Therefore, if a frequency division duplexing (FDD) transmission mode is adopted, a utilization rate of an upstream communication spectrum is low, and therefore, a time division duplexing (TDD) transmission mode is generated.
A TDD system uses a timeslot with a fixed width, upstream and downstream communication transmission uses a same frequency band, and the number of timeslots is assigned according to a service requirement of upstream communication or downstream communication; if there are a large number of services in the downstream communication, more timeslots is assigned for the downstream communication, and if there are a large number of services in the upstream communication, more timeslots is assigned for the upstream communication. A timeslot width of the TDD system corresponds to a TDD frame which is formed by a TDD timeslot guard interval and a valid payload. The timeslot guard interval includes signal delay such as a radio frequency circuit delay, carrier synchronization transition time, and radio frequency switch switching time, where the radio frequency circuit delay and the radio frequency switch switching time are a component fixed delay.
FIG. 1 is a schematic diagram of working principles of a TDD system in the prior art. As shown in FIGS. 1, A and B are two wireless TDD devices, and both of them have a TDD radio frequency switch and a synchronization module which performs carrier synchronization on a received signal. In a case that a valid data rate remains unchanged, flexibility of TDD timeslot assignment depends on the timeslot width, and the smaller the timeslot width is, the more flexible the assignment of upstream and downstream timeslots in the TDD system is. However, when a TDD timeslot width is reduced, and same a payload ratio needs to be kept, the timeslot guard interval needs to be reduced in equal proportion at the same time, that is, the carrier synchronization transition time needs to be reduced.
FIG. 2 is a schematic diagram of principles of a carrier synchronization process in the prior art. As shown in FIG. 2, in the prior art, a Costas loop is adopted to perform carrier synchronization, and two orthogonal local oscillation signals are adopted as feedback to be multiplied by a received two-phase shift keying (2PSK) signal, to obtain signals v3 and v4, respectively; the signals v3 and v4 undergo low-pass filtering in FIG. 2, to obtain signals v5 and v6, respectively. The signal v5 is multiplied by the signal v6 to obtain a signal v7. Loop filtering is performed on the signal v7 to obtain a carrier phase difference θ(t) between the local oscillation signals and the 2PSK signal. then a restored local oscillation signal, that is, a carrier signal, is obtained after processing performed by a voltage-controlled oscillator (VCO) in FIG. 2. The foregoing signal processing process needs to be performed for multiple times in carrier synchronization shown in FIG. 2, that is, the obtained carrier signal v1 needs to be further fed back, and undergoes the foregoing processing process repeatedly, and finally, an accurate carrier signal can be restored, and the more the feedback times are, the more accurate the obtained carrier signal is.
However, a Costas loop carrier synchronization circuit in the prior art has long carrier synchronization transition time, and cannot be used in fast carrier restoration in burst communication.